Method of manufacturing a MOSFET structure

ABSTRACT

A method of forming a MOSFET is provided. The method comprises forming a relatively thin layer of dielectric on a substrate. Depositing a gate material layer on the relatively thin layer of dielectric. Removing portions of the gate material layer to form a first and second gate material regions of predetermined lateral lengths. Introducing a first conductivity type dopant in the substrate to form a top gate using first edges of the first and second gate material regions as masks, Introducing a second conductivity dopant of high dopant density in the substrate to form a drain region adjacent the surface of the substrate using a second edge of the second gate material region as a mask to form a first edge of the drain region, wherein a spaced distance between the top gate and the drain region is determined by the lateral length of the second gate material region.

CROSS REFERENCE TO RELATED APPLICATION

Notice: More than one reissue application has been filed for the reissueof U.S. Pat. No. 7,687,336. These reissue applications includeapplication Ser. No. 13/235,000, filed on Sep. 16, 2011, and applicationSer. No. 13/590,856, filed on Aug. 21, 2012, which is a continuation ofapplication Ser. No. 13/235,000.

This is a Divisional Application of U.S. patent application Ser. No.11/234,344, filed on Sep. 29, 2005, which is a divisional of applicationof U.S. Pat. No. 6,974,753, filed Sep. 24, 2004, which is a divisionalapplication of U.S. Pat. No. 6,822,292, filed Nov. 21, 2001. Thisdivisional application is also related to U.S. Pat. No. 7,161,223, filedSep. 24, 2004. All of the above applications and patents areincorporated in there entirety by reference.

BACKGROUND

Integrated circuits incorporating high voltage lateral elements includeboth metal-oxide-semiconductor field-effect transistors (MOSFETs)devices and bipolar junction transistors. A common use of a power MOSFETin an integrated circuit is as an electronic switch. One knownhigh-voltage MOSFET structure for an integrated circuit includes a draincontact connected to the drain end of a channel by a lateral drainextension, which has the same conductively type as the drain contact.High voltage breakdown is achieved by designing the drain extension withan integrated doping (dopant ions per cm²) such that the drain extensiontotally depletes at high drain voltages, before the point whereavalanche breakdown occurs at a pn junction between the drain extensionand the MOSFET body.

Along with size of the structure, there are two other keycharacteristics of a MOSFET when used in an integrated circuit as anelectronic switch. The first is its breakdown voltage and the second isits ON resistance. The breakdown voltage is a measure of the MOSFET'sability to withstand a reversed bias voltage when it is in an OFF oropen condition. The ON resistance is a measure of the resistance whenthe MOSFET is in an ON or closed condition. Improving the operation ofthe MOSFET switch in an integrated circuit suggests a breakdown voltageas high as possible and an ON resistance as low as possible. A perfectswitching device has an infinite breakdown voltage and zero ONresistance. Accordingly, it is desired in the art to reduced the ONresistance. One way of reducing the ON resistance of a lateral MOSFETdevice is to accurately align various regions of the MOSFET to achievepredefined space between the regions. Unfortunately this is difficult todo with existing techniques because mask edges used to form the variousregions introduce an uncertainty factor called an alignment tolerancethat contributes to the space between the regions.

For the reasons stated above and for other reasons stated below whichwill become apparent to those skilled in the art there is a need for amethod of accurately controlling the distance between various regions inintegrated circuits.

SUMMARY

The above mentioned problems with integrated circuits with high voltageMOSFETs and other problems are addressed by the present invention andwill be understood by reading and studying the following specification.The following example summary is given by way of example not by way oflimitation.

In one embodiment, a method of forming a high voltage MOSFET for anintegrated circuit is provided. The method comprises forming arelatively thin layer of dielectric on a surface of a substrate.Depositing a gate material layer on the relatively thin layer ofdielectric. Removing portions of the gate material layer to form a firstand second gate material regions of predetermined lateral lengths.Introducing a first conductivity type dopant in the substrate to form atop gate using first edges of the first and second gate material regionsas masks, wherein the top gate is formed adjacent the surface of thesubstrate and laterally between the first and second gate materialregions. Introducing a second conductivity dopant of high dopant densityin the substrate to form a drain region adjacent the surface of thesubstrate using a second edge of the second gate material region as amask to form a first edge of the drain region, wherein the second gatematerial region is positioned laterally between the drain region and thetop gate and wherein the spaced distance between the top gate and thedrain region is determined by the lateral length of the second gatematerial region.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention can be more easily understood and the furtheradvantages and uses thereof more readily apparent, when considered inview of the description of the preferred embodiments and the followingfigures in which:

FIGS. 1 and 2 are cross-sectional views of prior art MOSFET devices;

FIG. 3 is a cross-sectional view of a MOSFET device of the prior art towhich the teachings of the present application can be applied;

FIGS. 4 through 10A illustrate, in a cross-section view, one embodimentof the present invention during sequential fabrication steps;

FIGS. 11 through 18A illustrate, in a cross-section view, embodiments ofthe present invention during sequential fabrication steps;

FIG. 19 is a cross-section view illustrating the use of gate material asa mask of one embodiment of the present invention;

FIG. 19A is a cross-sectional view illustrating drain and contactregions formed deeper than the top gate of one embodiment of the presentinvention;

FIG. 19B is a top view of one embodiment of a MOSFET of the presentinvention;

FIG. 19C is a top view of another embodiment of a MOSFET of the presentinvention;

FIG. 20 is a block diagram of a solid state relay incorporating MOSFETsof the present invention;

FIG. 21 is a cross-sectional view of a pn junction diode for anintegrated circuit of one embodiment of the present invention;

FIG. 21A is a top view of one embodiment of a pn junction diode for anintegrated circuit of the present invention; and

FIG. 22 is a cross-sectional view of a bipolar transistor for anintegrated circuit of one embodiment of the present invention.

In accordance with common practice, the various described features arenot drawn to scale but are drawn to emphasize specific features relevantto the present invention. Reference characters denote like elementsthroughout the Figures and text.

DETAILED DESCRIPTION

In the following detailed description of the preferred embodiments,reference is made to the accompanying drawings, which form a parthereof, and in which is shown by way of illustration specific preferredembodiments in which the inventions may be practiced. These embodimentsare described in sufficient detail to enable those skilled in the art topractice the invention, and it is to be understood that otherembodiments may be utilized and that logical, mechanical and electricalchanges may be made without departing from the spirit and scope of thepresent invention. The following detailed description is therefore, notto be taken in a limiting sense, and the scope of the present inventionis defined only by the claims and equivalents thereof.

Embodiments of the present invention relate to integrated circuitshaving relatively accurate aligned regions that are spaced apredetermined distance apart from each other. Moreover, some embodimentsof the present invention relate to integrated circuits having a MOSFETstructure with a drain region spaced apart from a top gate apredetermined distance. In the following description, the term substrateis used to refer generally to any structure on which integrated circuitsare formed, and also to such structures during various stages ofintegrated circuit fabrication. This term includes doped and undopedsemiconductors, epitaxial layers of a semiconductor on a supportingsemiconductor or insulating material, combinations of such layers, aswell as other such structures that are known in the art. Terms ofrelative position as used in this application are defined based on aplane parallel to the conventional plane or working surface of a waferor substrate, regardless of the orientation of the wafer or substrate.The term “horizontal” or “lateral” as used in this application isdefined as a plane parallel to the conventional plane or working surfaceof a wafer or substrate, regardless of the orientation of the wafer orsubstrate. The term “vertical” refers to a direction perpendicular tothe horizontal. Terms, such as “on”, “side” (as in “sidewall”), “right”,“left”, “higher”, “lower”, “over,” “top” and “under” are defined withrespect to the conventional plane or working surface being on the topsurface of the wafer or substrate, regardless of the orientation of thewafer or substrate. Before a detailed discussion of the embodiments ofthe present invention are described, further background is firstprovided to aid in the understanding of the embodiments of the presentinvention.

Referring to FIG. 1, a cross-sectional view of a known high voltagelateral MOSFET device 8 is illustrated. As illustrated, the MOSFETdevice 8 includes a gate 10, a source 12 with P+ doping concentrationand a drain 14. The drain 14 includes a P+ region 14a formed in a P−shield region 14b. The “+” indicates a high dopant density and the “−”indicates a low dopant density. The MOSFET device 8 further includes asilicon dioxide (SiO₂) layer 13 overlying the various active regions asshown. A body 11 of the device 8 is doped with a N-type dopant. A driftregion 17 or drain extension 17 is doped with a P type dopant andextends along the top surface of the body 11. The drain extension 17further has one edge adjacent to the P− shield region 14b. The driftregion 17 forms a portion of the conducting path between the source 12and the drain 14. A body contact 16 is also illustrated. In operation,the drain 14 is connected to a negative supply voltage, and the source12 and body 11 are connected together and further connected to apositive supply voltage. Typically, the drain 14 is connected to groundand a positive supply voltage is supplied to the shorted source 12/body11. More generally, the drain 14 is at a lower potential than theshorted source 12/body 11.

The drift region 17 serves as a JFET (function field-effect transistor)channel. A region 11a of the body 11, underlying the drift region 17provides a JFET gate function with respect to the channel of the driftregion 17. The drift region 17 is designed to totally deplete (i.e., apinch-off condition is created) at a voltage lower than the reverse biasvoltage at which avalanche breakdown occurs in the pn junction betweenthe drift region 17 and the body 11. The electric field of the fullydepleted drift region 17 is determined by the applied drain voltage. Theelectric field across the pn junction depends on the relativeconcentrations of the two doped regions and is maximum at themetallurgical junction between the regions. Thus most of the reversebias voltage is dropped across the depleted region. The length anddoping concentration of the drift region 17 determine the maximumelectric field that the drift region 17 can support. The source 12 andthe gate 10 are safely shielded from the high drain voltage by thepinched off depleted drift region 17.

The resistance of the drift region 17 is in series with the resistanceof the channel 11b, consequently, the total ON resistance of the device8 is simply the sum of these two individual resistances. The driftregion 17, which must be quite long to sustain the high reverse biasdrain-source voltage, often contributes the larger of the two resistanceterms, especially in high-voltage devices (for example, a drain-sourcevoltage greater than 100 V). Thus, it is desirable to reduce theresistance of the drift region 17 so that MOSFET devices can befabricated with lower channel ON resistance.

It is known that the drain extension resistance is inverselyproportional to the drain extension integrated doping. Thus, the ONresistance can be reduced by increasing the integrated doping level. Astructure and method that allows the extension integrated doping to beapproximately doubled without degrading the voltage characteristics,comprises the addition of a top gate and second extension of oppositeconductivity type to the first extension. The second extension is formedwithin the first extension. Such a dual lateral drain extension deviceis illustrated in commonly owned U.S. Pat. Nos. 4,823,173 and 5,264,719,which are both hereby incorporated by reference.

FIG. 2 illustrates such a prior art dual lateral drain extension DMOSFETdevice 48. The DMOSFET 48 includes a substrate 49 and an N type driftregion 50 disposed therein. The DMOSFET 48 further comprises an N+ drainregion 51 and a lateral P type top gate 53, both formed in the driftregion 50. An N+ source region 56 and a P+ substrate contact 58 are bothdisposed within a P type body 60. The DMOSFET device 48 furthercomprises a field oxide layer 61 and a gate 62 overlying a gate oxidelayer 64. The device channel is identified by a reference character 65and can be referred to as the MOS channel 65. The top gate 53 iselectrically connected to the substrate 49 in the third dimensionoutside the plane of FIG. 2.

The structure of FIG. 2 provides reduced ON resistance relative to theMOSFET device shown in FIG. 1 above. The reduction in ON resistance isaccomplished by providing a structure with increased drift region doping(the drift region 50) without reducing the body-to-drain reverse biasbreakdown voltage. This is made possible by inclusion of the top gate53, which serves as a JFET top gate. The depletion layer at the boundarybetween the top gate 53 and the drift region 50 holds some drift regioncharge when reverse biased, which is in addition to the charge held bythe depletion layer between a region 66 of the substrate 49, and thedrift region 50. Note that the region 66 serves as a JFET bottom gateand is electrically connected to the top gate 53 via the substrate 49.This additional charge, in the form of fixed ionized impurity atoms,causes the channel resistance reduction. It is possible to provideapproximately twice the integrated doping level in the drift region 50than previously acceptable due to this ability to hold drift regioncharge. The drift region 50 of the prior art has an exemplary integrateddoping of 1×10¹² phosphorous (or more generally n-type) atoms per squarecentimeter. Including the top gate 53 with an integrated doping of about1×10¹² ions per square centimeter, a doping level of 2×10¹² n-type atomsper square centimeter is possible in the drift region 50. Thus, the ONresistance in the FIG. 2 device is half the ON resistance of the priorstructures.

To optimize performance of the FIG. 2 structure, the top gate 53 shouldpreferably be designed differently than a conventional JFET gate. Thatis, the top gate 53 should totally deplete at a body-to-drain voltageless than the reverse bias breakdown voltage of the pn junction 68formed between the top gate 53 and drain region 51. The body-to-drainvoltage is used as a reference because the top gate 53 is in contactwith the body 49 in the third dimension outside the plane of FIG. 2.Therefore, the voltage at pn junction 68 equals the voltage at a pnjunction 70 formed between the drift region 50 and the body 49. Thevoltage at which pn junction 68 is designed to breakdown should begreater than the voltage at which the top gate 53 totally depletes.Further, the top gate 53 should totally deplete before the depletionlayer between the body 49 and the drift region 50 reaches the depletionlayer between the top gate 53 and the drift region 50. This conditionassures that a large voltage differential between the top gate 53 andthe drain region 51 is not developed by punch-through action from thebody 49. As is known by those skilled in the art, a conventional JFETgate (compared to the JFET action of the top gate 53) never totallydepletes regardless of operating conditions.

One method of fabricating the MOSFET 48 of FIG. 2 is to form the topgate 53 or both the drain drift region 50 and the top gate 53, after theMOSFET gate 62 has been formed. Using this technique, the JFET top gate53 can be self-aligned to the MOSFET gate 62 by using the latter as amask when the JFET top gate 53 is formed, preferably by ionimplantation. Process simulations of the MOSFET 48 of FIG. 2 indicate ahigh electric field at the junction between the drain contact 51 and thetop gate 53. Thus the reverse bias breakdown is more likely to occur atthe junction 68 than at other regions of the drain/body pn junction. Thehigh breakdown voltage characteristic may be recovered by spacing thetop gate 53 apart from the drain region 51 as illustrated by a MOSFET 90in FIG. 3. Simulations of the embodiment illustrated in FIG. 3, achievethe desired reverse bias breakdown voltage for MOSFET 90. Currentprocesses used to form the structure illustrated in FIG. 3 implementseparate mask steps that require alignment to define the distancebetween the top gate 53 and the drain region 51. However, extra masksteps, especially those requiring an alignment tolerance, areundesirable in the fabrication process as they increase the fabricationcost and protract fabrication time.

In particular, with current production processes, the edge of the drainregion 51 is defined by the location of an edge of an opening in a photoresist mask that serves to define where the drain region 51 is formed inthe substrate 49. Similarly, the edge of the top gate 53 is also definedby the location of an opening in another photo resist mask that definesthe location of the formation of the top gate 53. These two masks arealigned to a previous formed reference pattern. Thus there are twoalignment uncertainties between the edges of the photo resist masks thatdefine the edge of the drain region 51 and the edge of the top gateregion 53. Using projection aligners to perform the alignment of each ofthe photo resist masks to the previously formed reference pattern, asigma deviation from design location of the mask edge might be as highas 0.75×10⁻⁶ Since, the alignments of the drain region 51 and the topgate 53 are independent, the l sigma deviation from the nominal spacebetween their edges in this example would be:[(0.75)²+(0.75)²]^(0.5)=1.06×10⁻⁶.

The ON resistance of the MOSFET 90 of FIG. 3, is the sum of the variousseries resistances between the drain region 51 and the source region 56.This series resistance includes the drain region 51 and the sourceregion 56, plus the resistance of MOS channel 65, the resistance of thedrift region 50 (in particular the resistance of a JFET channel 67 inthe drift region 50 positioned beneath the JFET channel top gate 53) andthe link resistances between the JFET channel 67 under the top gate 53and the drain region 51 and between the JFET channel 50 under the topgate 53 and the MOS channel 65. Thus, one term in the ON resistance, thelink resistance from the JFET channel 67 to the drain region 51, isproportional to the length of the region 92 from an edge of the top gate53 to an adjacent edge of the drain contact 51. This distance alsoincreases the total device area. It is important to accurately controlthis length to minimize deviations in device area and ON resistance forMOSFETs constructed as illustrated in FIG. 3.

The above-mentioned undesirable variations associated with the spacingbetween the drain region and the JFET top gate can be reduced inaccordance with the teachings of the present invention. According to theteachings of the present invention, the distance between the drainregion and the top JFET gate is set without an alignment tolerance. Inaddition, the present invention reduces variations in the length ofregion 92 without the requirement of additional mask steps, therebyminimizing fabrication costs. Moreover, the present invention providesother novel teachings as disclosed and claimed below. The elements andmethod steps of the present invention are represented by conventionalelements in the drawings, showing only those specific details that arepertinent to the present invention, so as not to obscure the disclosurewith structural details that will be readily apparent to those skilledin the art having the benefit of the description herein.

The fabrication process for a MOSFET 100 of one embodiment the presentinvention begins with FIG. 4, wherein a relatively thick fielddielectric or oxide layer 116 is deposited, by chemical vapor depositionor thermally grown, on the upper surface 118 of the substrate 112. Asshown in FIG. 5, a portion of the relatively thick field oxide layer 116is removed by etching and a drift region 119 is formed by implantingdopants into the substrate 112 using the relatively thick oxide layer116 as a mask. Referring to FIG. 6, the remaining portion of the thickfield oxide layer 116 is removed and a dielectric layer is formed overthe substrate 112. In one embodiment, the dielectric is an oxide and thedielectric layer is referred to as an oxide layer. The oxide layercomprises a relatively thin oxide layer 120 and a thick oxide region121.

In one embodiment, the thin oxide layer 120 and thick oxide layer 121are formed by a local oxidation of silicon process (LOCOS) above thedrift region 110. In particular, the LOCOS process involves depositingsilicon nitrate (nitride) over a thin oxide layer that can be referredto as the pad oxide. The nitride is then patterned and removed fromareas where thick regions of oxide are to be grown. Although, not shownin the Figures, other devices formed in the integrated circuit besidesthe MOSFET 100 that require the formation of device regions userelatively thick regions of oxide as masks. These relatively thickregions are also formed at the same time by patterning the nitride layerin select locations. The substrate 112 is then subject to a thermaloxidation cycle which causes thick region 121 to be grown over the padoxide as well as other thick regions beyond the MOSFET 100 device notcovered by the nitride. Hence, the nitride acts as a mask in growing thethick regions of oxide during the thermal oxidation cycle. Once thethick regions of oxide have been grown, which include thick region 121,the remaining nitride and underlying pad oxide 120 are removed. The thinoxide layer 120 is then grown on the exposed surface 118 of thesubstrate 112 to form the structure as illustrated in FIG. 6.

In an alternative embodiment, the drift region 119 (drain extension 119)is formed using a mask before the thick oxide region 121 is formed. Inthis embodiment, after the drift region is formed, a layer of relativelythick oxide 116 is deposited over the entire surface 118 of thesubstrate 112. This is similar to that illustrated in FIG. 4. Portionsof the thick oxide layer 116 are then removed to form the thick region121. Other thick regions of oxide are also formed at this time for usein forming device regions for other devices in the integrated circuit(not shown). Moreover, these other thick regions (not shown) can be usedas masks to define the region comprising the MOSFET 100. Thereafter, thethin oxide layer 120 is grown. In one embodiment, the thin oxide layer120 is formed by oxidation of the substrate 112. The net result of thisembodiment is illustrated in FIG. 6.

As shown in FIG. 7, a poly silicon MOSFET gate 124 is depositedoverlying a portion of the relatively thin region 120. The MOSFET gate124 can be referred to as a gate 124, a gate electrode 124 or as gatematerial 124. A P type body 128 is formed by masking the remainder ofthe MOSFET 100 and implanting P type dopants through the thin oxide 120using the left edge of gate 124 as a self-aligned masked edge.

Referring to FIG. 8, a drain region 130 and a source region 132 areformed. The drain region 130 and the source region 132 are formed byimplanting N+ dopants through the thin oxide layer 120. In particular, asecond edge 152 of thick region 121 serves as a self-aligned mask duringformation of the drain region 130 to form a first edge 170 of the drainregion 130 and a photo resist mask is used to define a second edge 172of the drain region 130. In addition, a first edge 160 of MOSFET gate124 serves as a self-aligned mask during formation of the source region132 to form a second edge 182 of the source region 132 and the photoresist mask is used to define a first edge 180 of the source region 132.Typically, the drain region 130 and the source region 132 are formed atthe same time. FIG. 8 also illustrates a MOS channel region 133 withinthe P body 128.

As shown in FIG. 9, a P+ body contact 138 is formed in the P body 128 byimplanting high density P type dopants through the thin oxide layer 120.It is known by those skilled in the art that the source and drainregions 132 and 130, respectively, can be formed either before or afterformation of the P+ body contact 138. A P type dopant is implantedthrough the thin oxide layer 120 to form the top gate 140. A second edge162 of the MOSFET gate 124 and the first edge 150 of the relativelythick region 121 serve as self-aligned mask edges for forming the topgate 140. The width of the thick oxide region 121 is established tocreate the desired lateral spacing between the top gate 140 and thedrain region 130.

Referring to FIG. 10, a second layer of dielectric 125 is deposited onthe substrate 112 to provide another insulation layer. In one embodimentthe second layer of dielectric is a second layer of oxide 125. Selectedregions of the relatively thin oxide layer 120 and the second layer ofoxide 125 are etched and removed to form a first opening 127 adjacentthe body 128 and source 132 and a second opening 129 adjacent the draincontact 130. As illustrated in FIG. 10A, a body-source metal conductor131 is formed in the first opening 127 and a drain contact conductor 133is formed in the second opening 129. In one embodiment, the body-sourcemetal conductor 131 and the drain contact conductor 133 are made ofAluminum. Also illustrated, is a protective layer of passivation 135formed over the MOSFET 100.

The MOSFET 100 of FIG. 10, operates like MOSFET 90 of FIG. 3. Inparticular, the top gate 140 functions as a JFET top gate as does thetop gate 53 of FIG. 3. Moreover, region 142 of the substrate 112 servesas the JFET bottom gate 66 of FIG. 3. The process according to thepresent invention for creating the top gate 140 allows for accuratecontrol of the distance 148 shown in FIG. 10 without the requirement formask alignment tolerances and with few or no additional masking steps.

In another embodiment of the process according to the present invention,MOSFET 200 is fabricated. A relatively thick oxide layer 214 is firstformed overlying a substrate 212, as illustrated in FIG. 11. The fieldoxide layer 214 is patterned using conventional etch processes, tocreate a relatively thick oxide region 218, as illustrated in FIG. 12.Two drain drift regions 220 and 222 (or n type regions 220 and 222) areformed by implanting n type dopants into the substrate. In thisembodiment, the space between the first drift region 220 and the seconddrift region 222 is generally defined by the width of the relativelythick oxide region 218. In one embodiment, drift regions 220 and 222 areformed by masked diffusion. In this embodiment, during this diffusionprocess, the dopants diffuse laterally from the N type regions 220 and222, creating an overlap region 223 (or third N region 223) below therelatively thick oxide region 218, as illustrated in FIG. 12. Thiscreates a single main drain drift region 220, 222 and 233 that extendsfrom a gate electrode 230 past a drain contact 240. This is illustratedin FIG. 15. The drain contact 240 can be referred to as a drain region240.

Since, the dopant concentration in the overlap region 223 is created bylateral diffusion, it has a lower dopant concentration than that in then-type drift regions 220 and 222. Overlap region 223 therefore introducean undesirable region of high resistance within drift regions 220 and222. In one embodiment, this resistance is reduced by adding a N region260, as illustrated in FIG. 13. The overlap region 223 is positionedwithin the N region 260 as illustrated. Preferably N region 260 is one Nwell of several N wells formed at different locations within theintegrated circuit. Low voltage PMOS devices may then later be formed inthese other N wells in the integrated circuit. In this way, N region 260can be formed simultaneously with the formation of PMOS wells at otherlocations in the integrated circuit. N region 260 is formed prior to theformation of drift regions 220 and 222.

As also shown in FIG. 13, a relatively thin oxide layer 226 is thengrown on the substrate 212, which, as is know by those skilled in theart, also causes the thick region 218 to grow thicker, but at a slowerrate than the growth of new oxide. Referring to FIG. 14, a gate 230 isformed over a region of the relatively thin oxide layer 226. P typedopants are implanted and diffused through the relatively thin oxidelayer 226 to form a P type body region 232 in the P− substrate 212.

Referring to FIG. 15, a N+ drain region 240 and a N+ source region 244are formed by an implant of N+ dopants through the relatively thin oxideregion 226. In particular, a mask is used in forming a second edge 292of the N+ drain region 240 and a first edge 290 of the N+ drain regionis formed by the use of a second edge 282 of the relatively thick oxideregion 218 as a self-aligned mask. In addition, a mask is used to form afirst edge 274 of the N+ source region 244 and a first edge 270 of gate230 is used as a self-aligned mask to form a second edge 276 of the N+source region 244. As illustrated in FIG. 16, a P+ body contact region250 is formed in the P body region 232 by implanting P+ dopants throughthe relatively thin oxide layer 226.

A P type top gate 250 is formed by an implant of P type dopants throughthe relatively thin oxide layer 226. The top gate 250 is illustrated inFIG. 17. The top gate 250 is self-aligning to the first edge 280 of therelatively thick oxide region 218 and the second edge 272 of the gate230.

Referring to FIG. 18, a second layer of dielectric 251 is deposited onthe substrate 212 to provide another layer of insulation. In oneembodiment, the second layer of dielectric 251 is a second layer ofoxide 251. Selected regions of the relatively thin oxide layer 226 andthe second layer of oxide 251 are etched and removed to from a firstopening 253 adjacent the body 232 and the source 244 and a secondopening 255 adjacent the drain contact 240. A body-source conductor 257is formed in the first opening 253 and a drain conductor 259 is formedin the second opening 255. In one embodiment, the body-source conductor257 and the drain conductor 259 are made of Aluminum. Also illustratedis a protective layer of passivation 261 formed over MOSFET 200.

Referring to FIG. 18A, MOSFET 200 is illustrated a configurationtypically formed in an integrated circuit structure. In particular, FIG.18A illustrates two strips of a single multistripe device in anintegrated circuit. The N+ drain region 240 is a centerline 261 foradjacent top gates 250 and 250A. In this embodiment, a second thickregion 219 is formed to define the distance between the drain contact240 and top gate 250A the same way, and at the same time, the firstrelatively thick region 218 is formed. As illustrated, drift region 220is masked by the second thick region 219. However, when the N typedopents are introduced into the substrate 212 and diffused, overlapdrift region 225 under the second thick region 219 and drift region 227are formed, thereby creating a continuous single drift region thatcomprises drift regions 222, 223, 220, 225 and 227.

In one embodiment, the high resistance within overlap regions 223 and225 is reduced by adding a well 260 (or N region 260) of the secondconductivity type in the substrate, as illustrated in FIG. 18A. In thisembodiment, well 260 extends from top gate 250 to top gate 250A. Well260 is formed prior to the formation of N type regions 220, 222 and 227.Once well 260 is formed, the fabrication process continues with stepsillustrated in FIGS. 12 through 18.

Another embodiment of a MOSFET 300 is illustrated in FIG. 19. In thisembodiment, a JFET top gate 306A can be accurately spaced apart from thedrain region 308 using a strip of gate material. The strip of gatematerial is patterned to form the MOSFET gate 302A, a first gatematerial layer 302B and a second gate material layer 302C. In oneembodiment, the strip of gate material 302(A-C) comprises poly silicon.Gate material layers 302B and 302C serve as masks for the opposing edgesof the drain region 308 and gate layers 302A and 302B serve as masks toform the JFET top gate 306A. In one embodiment, a drain lateralextension 318 is formed, followed by formation of gate material layers302(A-C). Gate material layers 302B and 302C can be left floating sothat their potential is determined by capacitive coupling to adjacentmetal layers, or alternatively, they can be connected to the drainregion 308. This biasing of the gate material layers 302A and 302B,reduces degradation of breakdown of the MOSFET 300.

Following formation of gate material layers 302(A-C), processingcontinues with the various fabrication steps illustrated in FIGS. 7through 10. As illustrated in FIG. 19, the MOSFET 300 also includes asubstrate 316, a drift region 318, a body region 314, a body contact 312and a relatively thin layer of dielectric 310. In one embodiment, thelayer of dielectric 310 is a relatively thin layer of gate oxide 310. Inaddition, to minimize the area consumed by the gate material layers300(A-C) in an integrated circuit, the source and drain regions 304 and308 are typically constructed in alternating opposed orientations suchthat a centerline 322 of a multi-striped device passes through drainregion 308. Thus, with respect to FIG. 19, for a first strip of thedevice to the left of the centerline 322, drain region 308 is associatedwith top gate 306A and source region 304. For a second strip of thedevice to the right of the centerline 322, drain region 308 isassociated with top gate 306B. Moreover, the second strip of the deviceto the right of the centerline 322 will also have an associated sourceregion (not shown) to the right of top gate 306B.

With the fabrication process utilizing the gate material layers302(A-C), two alignment tolerances are removed from the process. Since,gate 302A and gate material layers 302B and 302C are formedsimultaneously by a single mask, the length of top gate 306A isestablished by the distance between gate 302A and gate material layer300B. Further, the width of the gate material layer 302B determines thespacing between the top gate 306A and the drain region 308. Thus twoalignment tolerances have been removed and the need for a separatemasking step to space the top gate 306A from the drain region 308 hasbeen eliminated. Moreover, in one embodiment, a strip of gate materialcan also be utilized in lieu of the thickened oxide region 218 of FIG.12, to form N type regions 220 and 222 in MOSFET 300.

In yet another embodiment of the invention, the need for a specificmasking step to form the JFET top gate 306A can be avoided by selectivedesign of the drain region 308, source region 304 and the JFET top gate306A. That is, a mask used to prevent the implantation of dopants usedto form top gate 306A in other areas of the substrate 316 can beeliminated by selective design. In particular, when drain region 308 andsource region 304 are formed deeper than the top gate 306A and also havea higher doping density at every depth than the top gate 306A, then amask is not required to form the latter. This is illustrated in FIG.19A. With this embodiment, the P type implant for forming the top gate306A can be permitted to diffuse into the drain region 308 and thesource region 304, where it will be overcompensated by the heavier anddeeper N+ concentration. If the top gate 306A is formed deeper than thedrain region 308 and the source region 304, and is permitted to diffuseinto the drain region 308, then the P diffusion will form a P type layerunder the N+ drain region 308. Thus the N+ drain region 308 is isolatedfrom the drain lateral extension 318, to which it must be ohmiclyconnected. Using this alternative process to form the drain region 318and the top gate 306A, eliminates one masked step from the fabricationsequence for the MOSFET device 300. This embodiment can also be appliedto MOSFET 100 of FIG. 10 and MOSFET 200 of FIG. 18A.

Referring back to FIG. 19, gate material layers 302B and 302C areillustrated as two separate areas. In one embodiment, however, a singlegate material region 313 is formed in an elliptical shape having acenter opening 309. In this embodiment, the gate material region 313includes gate material layers 302B and 302C. This is illustrated in FIG.19B. FIG. 19B is a top view of one embodiment of MOSFET 300. Asillustrated, the gate material region 313 is used to define the drainregion 308. That is, the drain region 308 is defined by an innerperimeter 323 of gate material 313. In addition, gate material 313defines the lateral space between the top gate 317 (which includes topgates 306A and 306B) and the drain region 308. Also illustrated in theembodiment of FIG. 19B, is the drain region 308 being shared on twosides by gates 302A, source regions 304 and body regions 314. Moreover,FIG. 19B also illustrates the top gate 317 extending around an outsideor outer perimeter 321 of gate material layers 302A and 302C (or gatematerial region 313). FIG. 19B also illustrates additional areas of topgate 303 that are present in the embodiment of FIG. 19A (the embodimentthat does not require a separate mask to form the top gate 306A). In oneembodiment, a relatively thick oxide layer is used in place of the gatematerial in gate material region 313. FIG. 19B also illustrates arelatively thick oxide region 383 surrounding MOSFET 300.

A top view of another embodiment of MOSFET 300 is illustrated in FIG.19C. In this embodiment, gate material region 381 includes gate materiallayers 302B and 302 C. In this embodiment the gate material region 381is formed in striped shape. Gate material region 381 has a centeropening 309 that defines the drain region 308. Moreover, the gatematerial region 381 defines the lateral distance between the drainregion 308 and the top gates 306A. Also illustrated in FIG. 19C aregates 302A, source regions 304 and body regions 314. In yet anotherembodiment, a relatively thick oxide layer is patterned and used inplace of the gate material in gate material region 381. FIG. 19C alsoillustrates a relatively thick oxide region 383 surrounding MOSFET 300.

As is known by those skilled in the art, there are many applications inintegrated circuits for the MOSFETs 100, 200 and 300 described herein.For example, they can be used as linear switches, solid state relays andtelecommunications switching circuits. In such applications, two DMOSFETdevices have their sources connected directly or through currentlimiting resistors and their drains serve as the output terminals of theswitch.

An embodiment of a solid state relay circuit 500 using a pair of DMOSFETdevices 502 and 504 as described above, is illustrated in FIG. 20. Asillustrated, the solid state relay circuit 500 includes a photo diodestack 506, a turn off and gate protection circuit 508 and two DMOSFETdevices 502 and 504 in an integrated circuit. The photo diode stack 506is used to drive voltage to the source S and gate G of each DMOSFET 502and 504. Generally, the photo diode stack 506 is illuminated by a lightemitting diode (not shown). The turn off and gate protection circuit 508is coupled in parallel with the photo diode stack 506 to discharge anygate-source capacitance when the photo diode is not driving voltage tothe source S and gate G of each DMOSFET 502 and 504. As illustrated,drain D of DMOSFET 502 is coupled to switch terminal S0. Moreover, drainD of DMOSFET 504 is coupled to switch terminal S0′.

Photo diodes in the photo diode stack 506 have open circuit voltage anda short circuit current when illuminated. A set of N photo diodes areconnected in series to form the photo diode stack 506. An open circuitvoltage of the diode stack will be N times the open circuit voltage of asingle photo diode. Moreover, the short circuit current of the photodiode stack 506 is equal to that of a single photo diode. Typically, anopen circuit voltage of approximately 0.4V and a short circuit currentof approximately 100 nA is produced by the solid state relay 500. A loadcomprising the gate capacitances of the two DMOSFET devices 502 and 504is coupled to the photo diode stack 506 in the solid state relay 500.The gate capacitance is shunted by the turn off and gate protectioncircuitry 508 coupled in parallel with the photo diode stack 506. Anequilibrium gate source voltage of the DMOSFET devices 502 and 504 in anoff condition is 0V.

When the light emitting diode is turned on, illuminating the photo diodestack 506, the short circuit current of the photo diode stack 506 beginsto charge the gate capacitance of DMOSFET devices 502 and 504. Agate-source voltage of each DMOSFET devices 502 and 504 rises as therespective gate capacitance charges until reaching the stack opencircuit voltage. The number of photo diodes in the photo diode stack 506is chosen such that its open circuit voltage is larger that thethreshold voltages of the DMOSFET devices 502 and 504. Consequently, theDMOSFET devices 502 and 504 turn on when the stack is illuminatedthereby presenting the ON resistance of the DMOSFET devices 502 and 504in series with the switch terminals S0 and S0′.

DMOSFET device 502 and 504 are coupled in series to form a switch toblock relatively large voltages, of both polarities, across the switchterminals S0 and S0′ when the switch is off. This exploits the fact thatthe DMOSFET devices 502 and 504 each have asymmetric breakdown with thedrain to source breakdown being relatively large while the source todrain breakdown is relatively small (often as small as a diode forwardvoltage). By having the DMOSFET devices 502 and 504 coupled in series,the drains D of the devices 502 and 504 are coupled to their associatedswitch terminals S0 and S0′. When switch terminal S0 has a positivevoltage that is more positive than the voltage on switch terminal S0′,the drain junction of the DMOSFET device 502 blocks the applied voltage.Moreover, when switch terminal S0′ has a positive voltage that is morepositive that the voltage on switch terminal S0, the drain junction ofDMOSFET device 504 blocks the applied voltage.

Turn off of the solid state relay 500 is initialized when the LED isturned off. An output current of the photo diode stack 506 then goes to0V. The turn off and gate protection circuit 508, which in its simplestform may comprise a relatively large resistor, discharges the gatecapacitance of gate G of the DMOSFET devices 502 and 504 thereby takingthe gate source voltage back to 0V on both DMOSFET devices 502 and 504.

The teachings of the present invention can also be applied to thefabrication of pn junction diodes in integrated circuits that arefabricated with a diffusion region 356, as illustrated in FIG. 21. Theembodiment illustrated in FIG. 21, shows a substrate 348 and a pnjunction diode 340 formed in substrate 348 of the integrated circuit.The pn junction diode 340 comprises a cathode contact 350 (doped N+) andtwo P+ anode contact regions 352 and 354 in an anode 348 (the substrate348). A cathode 356 and two JFET top gate regions 358 and 360 are alsoillustrated. As illustrated, the cathode 356 extends laterally from aportion of top gate 358 to a portion of top gate 360. With respect tothe individual P− and N type regions, they function in a manneridentical to their function in the MOSFET devices discussed above.

The teachings of the present invention offer a fabrication techniquethat eliminates masked alignment tolerances and provides a relativelyaccurate length for the regions 362 and 364, which are disposed betweenthe cathode contact 350 and the top gates 358 and 360, respectively.Thus, the technique described with respect to FIGS. 4 through 10(teaching the use of a thick oxide region as a mask, thick oxide regions359 and 361 of FIG. 21), FIGS. 11 through 18A (teaching the use of twooverlapping n-type diffusions to form a drift region 356, which in thiscase is a N type cathode region 356) and FIG. 19-19A (teaching the useof a gate layer material as a mask instead of a relatively thick oxideor dielectric layer) can be applied to the structure of FIG. 21. As isknown by those skilled in the art, the structure of FIG. 21 can also bemodified such that the JFET top gates 358 and 360 overlap or abut the P+anode contact regions 352 and 354, respectively.

Referring to FIG. 21A a top view of one embodiment of a pn junctiondiode 340 is illustrated. As illustrated, in this embodiment, thickoxide region 363 includes thick oxide regions 359 and 361. Inparticular, ends of the thick oxide regions 359 and 361 are connectedtogether when formed to create a single thick oxide region 363 with acentral opening 383. In the embodiment shown, the thick oxide region 363is formed in an elliptical shape. Moreover, thick oxide region 362defines the cathode contact 350. In particular an inner perimeter 385 ofthe thick oxide region 363 defines the cathode contact 350. In addition,the thick oxide region 363 also defines the lateral distance between thecathode contact 350 and top gate region 355. In this embodiment, topgate region 355 includes top gate regions 358 and 360 of FIG. 21. Thatis, top gate regions 358 and 360 form the single top gate region 355.Top gate region 355 extends around an outer perimeter 387 of the thickoxide region 355. Also shown in FIG. 21A are the anode contact regions352 and 354. In one embodiment, top gate regions 370 and 372 are alsoincluded. In addition, as illustrated, a layer of relatively thick oxide380 surrounds the pn junction diode 340.

The teachings of the present invention can also be applied to a highvoltage PNP bipolar junction transistor 401 formed in an integratedcircuit as illustrated in FIG. 22. The transistor regions are formed ina substrate 399 of the integrated circuit and comprise a base contact400 and an emitter 402 disposed within a base region 404. An extensionregion 406 (which in one embodiment can be made shallower than the baseregion 404) is also illustrated. The transistor 401 also comprises twop-type extension regions or JFET top gates 410 and 412. The JFET topgates 410 and 412 are actually separate parts of a single gate that isformed in a semi-circular shape in the substrate 399. A collectorcontact 414 is also shown. The teachings of the present inventions asdiscussed above can be advantageously utilized to accurately space thebase region 404 from the P-type extension 410 and 412. In particular,FIGS. 4 through 10 (which teach the use of a relatively thick dielectricregion as a mask to accurately dimension the distances 416 and 418 ofFIG. 22). FIG. 22 illustrates relatively thick dielectric regions 419and 421 of the PNP junction transistor 401. The relatively thickdielectric regions 419 and 421 are actually separate parts of a singlerelatively thick dielectric region that is formed into a semi-circularshape to define the base region 404. Other teachings of the presentinvention as discussed above can also be advantageously utilized inoverlapping N type diffusions (as illustrated in FIGS. 11-18A) and usingof a gate material layer as a mask (as illustrated in FIGS. 19-19A).Although FIG. 22 illustrates a PNP bipolar junction transistor 401,those skilled in the art recognize that the teachings of the presentinvention can also be applied to an NPN bipolar transistor of anintegrated circuit.

While the invention has been described with reference to preferredembodiments, it will be understood by those skilled in the art thatvarious changes may be made and equivalent elements may be substitutedfor elements thereof without departing from the scope of the presentinvention. In addition, modifications may be made to the teachings ofthe invention to adapt it to a particular situation, without departingfrom the essential scope thereof. Therefore, it is intended that theinvention not be limited to the particular embodiment disclosed as thebest mode contemplated for carrying out this invention, but that theinvention would include all embodiments falling within the scope of theappended claims.

What is claimed is:
 1. A method of forming a high voltage MOSFET for anintegrated circuit, the method comprising: forming a relatively thinlayer of dielectric on a surface of a substrate; depositing a gatematerial layer on the relatively thin layer of dielectric; removingportions of the gate material layer to form first and second gatematerial regions of predetermined lateral lengths; introducing a firstconductivity type dopant in the substrate to form a top gate using firstedges of the first and second gate material regions as masks, whereinthe top gate is formed adjacent the surface of the substrate andlaterally between the first and second gate material regions;introducing a second conductivity dopant of high dopant density in thesubstrate to form a drain region adjacent the surface of the substrateusing a second edge of the second gate material region as a mask to forma first edge of the drain region, wherein the second gate materialregion is positioned laterally between the drain region and the topgate; and wherein the spaced distance between the top gate and the drainregion is determined by the lateral length of the second gate materialregion.
 2. The method of claim 1, wherein the drain region is formed toextend deeper from the surface of the substrate than the top gate,further wherein the drain region is formed with a higher doping densityat every depth than the top gate.
 3. The method of claim 1, wherein theremoving of portions of the gate material layer further forms a thirdgate material region of a predetermined lateral length, wherein a edgeof the third gate material region is used as a mask to form a secondedge of the drain region.
 4. The method of claim 3, wherein the secondand third gate material regions are left floating.
 5. The method ofclaim 3, further comprising: coupling the second and third gate materialregions to the drain region.
 6. The method of claim 3, wherein the thirdgate material region is connected to the second gate material region,the second and third gate material regions forming a central opening,wherein the drain region is formed through the central opening.
 7. Themethod of claim 1, further comprising: introducing the secondconductivity type dopant of high density to the substrate to form asource region adjacent the first gate material region, wherein the firstgate material region is generally positioned laterally between thesource region and the top gate.
 8. The method of claim 7, wherein anedge of the first gate material region is used as a mask to form an edgeof the source region.
 9. The method of claim 7, further comprising:introducing the first conductivity type dopant to the substrate to forma body region, the body region being positioned adjacent the surface ofthe substrate and the source; and introducing a first conductivitydopant of a high density in the body region to form a body contact,wherein the body contact is positioned adjacent the surface of thesubstrate and a portion of the source.
 10. The method of claim 1,further comprising: forming a first drift region of a secondconductivity type dopant in the substrate using a first edge of thesecond gate material region as a mask; and forming a second drift regionof the second conductivity type dopant in the substrate using a secondedge of the second gate material region as a mask.
 11. The method ofclaim 10, further comprising: diffusing the first and second driftregions to form an overlap third region under the second gate materialregion.
 12. The method of claim 10, further comprising: forming a wellregion in the substrate of the second conductivity type to reduceresistance within the first and second drift regions, wherein portionsof the first and second drift regions are formed in the well.
 13. Themethod of claim 10, wherein the first and second drift regions arespaced apart from each other by the width of the second gate materialregion.
 14. A method of forming a lateral MOSFET in an integratedcircuit, the method comprising: forming a drain contact of a secondconductivity type with a high density dopant in a substrate adjacent asurface of the substrate; forming a top gate of a first conductivitytype in the substrate adjacent the surface of the substrate and apredetermined distance from the drain contact after the drain contact isformed; and wherein the drain contact is formed to extend deeper fromthe surface of the substrate than the top gate and is formed to have ahigher dopant density at every depth than the top gate so a mask is notneeded to shield the drain contact from the first conductivity dopantsduring formation of the top gate.
 15. The method of claim 14, furthercomprising: forming a relatively thin dielectric layer on a surface of asubstrate, the substrate being of a first conductivity type with a lowdopant density; and depositing a gate on the surface on the relativelythin dielectric layer.
 16. The method of claim 14, further comprising:forming a source of the second conductivity type with a high dopantdensity in the substrate approximate the gate, wherein the source isformed to extend deeper from the surface of the substrate than the topgate and is formed to have a higher dopant density at every depth thanthe top gate so a mask is not needed to shield the source from the firstconductivity dopants during formation of the top gate.
 17. The method ofclaim 14, wherein forming the distance between the drain contact and thetop gate further comprises: forming a relatively thick layer of materialhaving a predetermined lateral length on the surface of the substrate;introducing high density dopants of the second conductivity type to thesubstrate to form the drain contact, wherein a first edge of therelatively thick layer of material defines a first edge of draincontact; and introducing dopants of the first conductivity type to thesubstrate to form the top gate, wherein a second edge of the relativelythick layer of material defines a first edge of the top gate, furtherwherein the distance between the top gate and the drain contact isdefined by the lateral length of the relatively thick layer of material.18. The method of claim 17, wherein the relatively thick layer ofmaterial is a layer of dielectric.
 19. The method of claim 17, whereinthe relatively thick layer of material is a layer of gate material. 20.A device comprising: a substrate having a surface; a relatively thinlayer of dielectric material on the surface of the substrate; arelatively thick layer of dielectric material on the surface of thesubstrate adjacent to the relatively thin layer of dielectric material;a drain region of a first conductivity type with a higher dopant densityin the substrate adjacent to the surface of the substrate; and a driftregion of the first conductivity type with a lower dopant density in thesubstrate adjacent to the surface of the substrate, the drift regioncomprising a first portion having a junction depth less than thejunction depths of adjacent portions on opposite sides of the firstportion.
 21. The device of claim 20, wherein the first portion of thedrift region has a lower dopant density than the adjacent portions onopposite sides of the first portion.
 22. The device of claim 20, whereinthe first portion of the drift region is located below the relativelythick layer of dielectric material.
 23. The device of claim 20, whereinthe first portion of the drift region comprises overlapped diffusededges of a first conductivity type dopant.
 24. The device of claim 20,wherein the first portion of the drift region comprises overlappeddiffused edges of a first conductivity type dopant masked by therelatively thick layer of dielectric material.
 25. The device of claim20, wherein the drain region has an edge defined by an edge of therelatively thick layer of dielectric material.
 26. The device of claim20, further comprising a gate region on the relatively thin layer ofdielectric material.
 27. The device of claim 20, further comprising abody region of a second conductivity type in the substrate adjacent tothe surface of the substrate.
 28. The device of claim 27, furthercomprising a source region of the first conductivity type with a higherdopant density in the body region.
 29. The device of claim 28, furthercomprising a body contact of the second conductivity type with a higherdopant density in the body region adjacent to the source region.
 30. Adevice comprising: a first dielectric layer on a surface of a substrate;a second dielectric layer on the surface of the substrate adjacent tothe first dielectric layer, the second dielectric layer having athickness greater than the thickness of the first dielectric layer; adrain region of a first conductivity type in the substrate adjacent tothe surface of the substrate; and a drift region of the firstconductivity type in the substrate adjacent to the surface of thesubstrate, the drift region comprising a first portion having a lowerdoping density than the doping densities of adjacent portions onopposite sides of the first portion.
 31. The device of claim 30, furthercomprising a gate region on the first dielectric layer.
 32. The deviceof claim 30, further comprising a body region of a second conductivitytype in the substrate adjacent to the surface of the substrate.
 33. Thedevice of claim 32, further comprising a source region of the firstconductivity type in the body region.
 34. The device of claim 33,further comprising a body contact of the second conductivity type in thebody region adjacent to the source region.